The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to methods of lithographic patterning.
A back-end-of-line (BEOL) interconnect structure may be used to electrically couple device structures fabricated on a substrate during front-end-of-line (FEOL) processing. The BEOL interconnect structure may be formed using a dual-damascene process in which via openings and trenches etching in a dielectric layer are simultaneously filled with metal to create a metallization level. In a via-first, trench-last dual damascene process in which via openings are formed in a dielectric layer and then a trench is formed in the dielectric layer above the via openings, the via openings are unfilled during the etching process forming the trenches. In a single-damascene process, the via openings and trench are formed in different dielectric layers and filled separately with metal.
Self-aligned patterning processes involve the use of mandrels as sacrificial structures. Sidewall spacers, which have a thickness less than that permitted by the current ground rules for optical lithography, are formed on the vertical sidewalls of the mandrels. After selective removal of the mandrels, the sidewall spacers are used as an etch mask to etch an underlying hardmask and dielectric layer, for example, with a directional reactive ion etching (RIE). Because the sidewall spacers may have a sublithographic line pitch and width, the features formed in underlying dielectric layer will also have a sublithographic line pitch and width.
Cuts may be formed in mandrels with a cut mask and etching in order to section the mandrels and define gaps that subsequently are used to form adjacent wires that are spaced apart at their tips with a tip-to-tip spacing. The pattern of the cut mandrels is transferred to a hardmask used to pattern a dielectric layer. Cuts may also be formed in the hardmask itself and filled by spacer material when sidewall spacers are formed on the mandrels. These cuts are also transferred to the hardmask and are reflected in the patterned dielectric layer.
Improved methods of lithographic patterning are needed.